US 12,418,265 B2
Direct substrate to solder bump connection for thermal management in flip chip amplifiers
Michael Joseph McPartlin, North Andover, MA (US); Bharatjeet Singh Gill, Ottawa (CA); and Stephen Joseph Kovacic, Newport Beach, CA (US)
Assigned to Skyworks Solutions, Inc., Irvine, CA (US)
Filed by Skyworks Solutions, Inc., Irvine, CA (US)
Filed on Oct. 24, 2022, as Appl. No. 17/971,854.
Application 17/971,854 is a continuation of application No. 17/009,129, filed on Sep. 1, 2020, granted, now 11,515,845.
Application 17/009,129 is a continuation of application No. 16/056,251, filed on Aug. 6, 2018, granted, now 10,790,788, issued on Sep. 29, 2020.
Application 16/056,251 is a continuation of application No. 15/299,738, filed on Oct. 21, 2016, granted, now 10,069,466, issued on Sep. 4, 2018.
Claims priority of provisional application 62/245,168, filed on Oct. 22, 2015.
Claims priority of provisional application 62/245,183, filed on Oct. 22, 2015.
Prior Publication US 2023/0155555 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 1/30 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/36 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/66 (2006.01); H01L 25/00 (2006.01); H03F 1/56 (2006.01); H03F 3/195 (2006.01); H03F 3/21 (2006.01); H03F 3/213 (2006.01); H03F 3/24 (2006.01); H04B 1/04 (2006.01); H04B 1/44 (2006.01); H04B 1/48 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/60 (2025.01)
CPC H03F 1/302 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4882 (2013.01); H01L 23/3114 (2013.01); H01L 23/3142 (2013.01); H01L 23/3157 (2013.01); H01L 23/36 (2013.01); H01L 23/367 (2013.01); H01L 23/3675 (2013.01); H01L 23/3736 (2013.01); H01L 23/3738 (2013.01); H01L 23/49816 (2013.01); H01L 23/49844 (2013.01); H01L 23/5223 (2013.01); H01L 23/528 (2013.01); H01L 23/5286 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/66 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 25/50 (2013.01); H03F 1/56 (2013.01); H03F 3/195 (2013.01); H03F 3/211 (2013.01); H03F 3/213 (2013.01); H03F 3/24 (2013.01); H03F 3/245 (2013.01); H04B 1/0475 (2013.01); H04B 1/44 (2013.01); H04B 1/48 (2013.01); H10D 84/0112 (2025.01); H10D 84/038 (2025.01); H10D 84/615 (2025.01); H01L 2223/6655 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/1302 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13647 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81447 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10271 (2013.01); H01L 2924/1207 (2013.01); H01L 2924/1305 (2013.01); H03F 2200/387 (2013.01); H03F 2200/447 (2013.01); H03F 2200/451 (2013.01)] 22 Claims
OG exemplary drawing
 
13. An semiconductor die comprising:
a semiconductor substrate;
a first transistor formed over the semiconductor substrate;
a first metal structure positioned with respect to the semiconductor substrate such that a first end of the first metal structure is in thermal communication with the semiconductor substrate, the first metal structure forming part of a first die contact; and
a first resistor in electrical communication with an emitter of the first transistor and with the first metal structure, heat generated during operation of the first transistor being transferred the first metal structure.