US 12,418,005 B2
Semiconductor package and manufacturing method thereof
Tzuan-Horng Liu, Taoyuan (TW); Hao-Yi Tsai, Hsinchu (TW); Kris Lipu Chuang, Hsinchu (TW); and Hsin-Yu Pan, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 4, 2022, as Appl. No. 17/880,687.
Prior Publication US 2024/0047436 A1, Feb. 8, 2024
Int. Cl. H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 24/16 (2013.01); H01L 24/20 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/214 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/73267 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first die disposed on and electrically coupled to a first redistribution structure, and the first die laterally covered by a first insulating encapsulation;
a second die disposed over the first die and laterally covered by a second insulating encapsulation;
a second redistribution structure interposed between and electrically coupled to the first and second dies, and through substrate vias of the first die being physically connected to the second redistribution structure or the first redistribution structure;
a third redistribution structure disposed on the second die and opposite to the second redistribution structure, the third redistribution structure comprising a patterned conductive layer embedded in a dielectric layer, the patterned conductive layer comprising a conductive via disposed in a first level of the dielectric layer and a conductive pad disposed over the conductive via and disposed in a second level of the dielectric layer; and
at least one thermal-dissipating feature embedded in the dielectric layer of the third redistribution structure and electrically isolated from the patterned conductive layer through the dielectric layer of the third redistribution structure, and the at least one thermal-dissipating feature thermally coupled to a back surface of the second die, wherein the at least one thermal-dissipating feature comprises a thermal-dissipating via disposed in the first level of the dielectric layer and a thermal-dissipating pattern disposed over the thermal-dissipating via and disposed in the second level of the dielectric layer.