US 12,417,991 B2
Chip stack structure with conductive plug and method for forming the same
Chuei-Tang Wang, Taichung (TW); Tso-Jung Chang, Taoyuan (TW); Shih-Ping Lin, Taichung (TW); Jeng-Shien Hsieh, Kaohsiung (TW); Chih-Peng Lin, Hsinchu County (TW); Chieh-Yen Chen, Taipei (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 6, 2023, as Appl. No. 18/150,949.
Claims priority of provisional application 63/433,261, filed on Dec. 16, 2022.
Prior Publication US 2024/0203918 A1, Jun. 20, 2024
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/08 (2013.01) [H01L 24/80 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip stack structure, comprising:
a first chip comprising a first substrate and a first interconnect structure over the first substrate, wherein the first interconnect structure comprises a first dielectric layer and a first bonding pad embedded in the first dielectric layer;
a second chip over and bonded to the first chip, wherein the second chip has a second interconnect structure and a second substrate over the second interconnect structure, the second interconnect structure is wider than the second substrate, the second interconnect structure comprises a second dielectric layer and a second bonding pad embedded in the second dielectric layer, the first bonding pad is in direct contact with the second bonding pad, and the first dielectric layer is in direct contact with the second dielectric layer;
an insulating layer over the second interconnect structure and surrounding the second substrate; and
a conductive plug penetrating through the insulating layer to the second interconnect structure.