| CPC H01L 23/49811 (2013.01) [H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49844 (2013.01); H01L 24/48 (2013.01); H01L 25/072 (2013.01); H01L 2224/48155 (2013.01); H01L 2224/48175 (2013.01); H01L 2224/48225 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/30107 (2013.01)] | 5 Claims |
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1. A low parasitic inductance power module featuring staggered interleaving conductive members, comprising:
at least one electrically insulative base extending along a length direction;
a substrate provided with at least one current input bus bar along a width direction which is perpendicular to the length direction and at least one current output bus bar which is parallel to the current input bus bar and electrically insulated from the current input bus bar;
a first unit comprising a first circuit base portion disposed at the electrically insulated base along the width direction perpendicular to the length direction, on the first circuit base portion being disposed a plurality of first power devices, each of the first power devices having a first current input terminal and a first current output terminal, the first current input terminals of the first power devices being parallel connected with each other, the first current output terminals of the first power devices being parallel connected with each other; wherein the first current input terminals are conductively mounted to the first circuit base portion, or alternatively, the output terminals are conductively mounted to the first circuit base portion;
a second unit comprising a second circuit base portion which is disposed at the electrically insulated base along the width direction perpendicular to the length direction and spaced apart from the first circuit base portion in the length direction, on the second circuit base portion being disposed a plurality of second power devices, each of the second power devices having a second current input terminal and a second current output terminal, the second current input terminals of the second power devices being parallel connected with each other, the second current output terminals of the second power devices being parallel connected with each other; wherein the second current input terminals are conductively mounted to the second circuit base portion, or alternatively, the second current output terminals are conductively mounted to the second circuit base portion;
wherein the first unit and the second unit are serially connected via their respective one ends along the length direction through a plurality of mutually staggered arrayed serially-connected conductive members, the other end of the first unit opposite the one end thereof is serially connected to the current input bus bar through a plurality of mutually staggered arrayed input conductive members, and the other end of the second unit opposite the one end thereof is serially connected to the current output bus bar through a plurality of mutually staggered arrayed output conductive members; wherein when lengthwise projections of the serially-connected conductive members, the input conductive members, and the output conductive members overlap, their projections in the width direction are arrayed in a staggered interleaving mode, and/or their projections overlap with each other in a height direction perpendicular to the length direction and the width direction, whereby when current flows through the staggered serially-connected conductive members, the staggered input conductive members, and the staggered output conductive members, individual inductances are countered with each other, reducing the overall parasitic inductance.
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