US 12,417,963 B2
Isolation rail between backside power rails
Nicholas Anthony Lanzillo, Wynantskill, NY (US); Lawrence A. Clevenger, Saratoga Springs, NY (US); Hosadurga Shobha, Niskayuna, NY (US); Ruilong Xie, Niskayuna, NY (US); and Baozhen Li, South Burlington, VT (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Oct. 24, 2022, as Appl. No. 18/048,877.
Prior Publication US 2024/0136253 A1, Apr. 25, 2024
Prior Publication US 2024/0234248 A9, Jul. 11, 2024
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01)
CPC H01L 23/481 (2013.01) [H01L 21/76877 (2013.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
one or more integrated circuit (IC) microdevices upon the substrate, the one or more IC microdevices include a first node and a second node;
a first backside contact connected to a portion of a bottom surface of the first node and a second backside contact connected to a portion of a bottom surface of the second node;
a backside power rail connected to the first backside contact and a backside ground rail connected to the second node; and
a backside isolation rail between the backside power rail and the backside ground rail.