US 12,417,943 B2
Reducing intralevel capacitance in semiconductor devices
Joseph R. Abel, West Linn, OR (US); Bart J. Van Schravendijk, Palo Alto, CA (US); Ian John Curtin, Portland, OR (US); Douglas Walter Agnew, Portland, OR (US); Dustin Zachary Austin, Tigard, OR (US); and Awnish Gupta, Hillsboro, OR (US)
Assigned to Lam Research Corporation, Fremont, CA (US)
Appl. No. 18/003,145
Filed by Lam Research Corporation, Fremont, CA (US)
PCT Filed Jun. 28, 2021, PCT No. PCT/US2021/039444
§ 371(c)(1), (2) Date Dec. 22, 2022,
PCT Pub. No. WO2022/006010, PCT Pub. Date Jan. 6, 2022.
Claims priority of provisional application 62/705,506, filed on Jun. 30, 2020.
Prior Publication US 2023/0307290 A1, Sep. 28, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/0228 (2013.01); H01L 21/76814 (2013.01); H01L 21/76837 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a structure comprising features and an open gap between the features, the open gap including sidewall and bottom surfaces and having a depth; and
performing one or more inhibition blocks, each inhibition block comprising:
a) exposing the structure to an inhibition treatment to inhibit dielectric deposition on the sidewall and bottom surfaces of the gap, and
b) selectively depositing dielectric film near the top of the gap without significant deposition near the bottom surface of the gap.