US 12,417,817 B1
Stacked 3D memory architecture for power optimization
Ahmad Abdel Rauof Samih, Austin, TX (US); Daniel Henry Morris, Mountain View, CA (US); Hadi Asgharimoghaddam, Kirkland, WA (US); Pietro Caragiulo, Palo Alto, CA (US); Vamshi Krishna Lakkaraju, Chandler, AZ (US); and Vivek Venkatesan, Pleasanton, CA (US)
Assigned to Meta Platforms Technologies, LLC, Menlo Park, CA (US)
Filed by Meta Platforms Technologies, LLC, Menlo Park, CA (US)
Filed on Apr. 11, 2023, as Appl. No. 18/298,779.
Int. Cl. G11C 11/00 (2006.01); G06F 13/16 (2006.01); G11C 29/00 (2006.01)
CPC G11C 29/83 (2013.01) [G06F 13/1668 (2013.01); G11C 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A headset, comprising:
a camera;
a 3D stacked memory configured to store image data captured by the camera, the 3D stacked memory having a plurality of first drivers/receivers and a plurality of memory banks that are accessible in parallel, wherein each memory bank is accessible via a corresponding first driver/receiver; and
a System-on-Chip (SoC) configured to process the image data stored in the 3D stacked memory, the SoC having a memory controller with a plurality of second drivers/receivers, wherein the plurality of the second drivers/receivers are respectively connected to the plurality of the first drivers/receivers of the 3D stacked memory by a plurality of channels,
wherein:
the SoC and the 3D stacked memory are vertically stacked together;
the plurality of the memory banks each has a page size of 512 bytes or less;
the plurality of the memory banks include at least eight memory banks; and
the plurality of the channels are controlled by unidirectional and/or bidirectional links.