US 12,417,813 B2
Memory device for outputting test results
Jongpil Son, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 7, 2022, as Appl. No. 18/062,843.
Claims priority of application No. 10-2021-0175215 (KR), filed on Dec. 8, 2021; and application No. 10-2022-0056242 (KR), filed on May 6, 2022.
Prior Publication US 2023/0178169 A1, Jun. 8, 2023
Int. Cl. G11C 11/34 (2006.01); G11C 29/00 (2006.01); G11C 29/18 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/4401 (2013.01) [G11C 29/18 (2013.01); G11C 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array comprising a plurality of memory cells arranged at intersections of a plurality of rows, and a plurality of columns and redundancy memory cells configured to repair a failed memory cell from among the memory cells; and
a repair circuit configured to perform a repair operation on the failed memory cell, and output a dirty signal to an external destination external to the memory device, the repair operation including,
selecting a first redundancy address of the redundancy memory cells instead of a first fail address of a first failed memory cell,
storing a first redundancy mapping for the first fail address to the first redundancy address, and,
in response to determining a second fail address of a second failed memory cell matches the first redundancy address,
ignoring the first redundancy mapping, and
outputting the dirty signal causing a second redundancy mapping to map the first fail address to a second redundancy address different from the first redundancy address of the redundancy memory cells.