US 12,417,812 B2
Failure analysis device and failure analysis method
Toru Ogushi, Tokyo (JP); Sho Uesugi, Tokyo (JP); and Yukihisa Funatsu, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on Sep. 29, 2023, as Appl. No. 18/478,207.
Prior Publication US 2025/0111882 A1, Apr. 3, 2025
Int. Cl. G11C 29/10 (2006.01); G11C 29/18 (2006.01); G11C 29/38 (2006.01)
CPC G11C 29/10 (2013.01) [G11C 29/18 (2013.01); G11C 29/38 (2013.01); G11C 2029/1806 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A failure analysis device for analyzing a failure of a semiconductor having a logic circuit and a memory circuit, comprising:
a storage device for storing fail bit data obtained by testing the memory circuit, and failure diagnosis data obtained by failure diagnosis for the test results of the logic circuit, and
a processor,
wherein the processor extracts a fail I/O from the fail bit data, and extracts data of a memory connection port which is a connection port to the memory circuit from an estimated failure part included in the failure diagnosis data, and determines whether the fail I/O and a port ID included in the data of the memory connection port match or not.