US 12,417,811 B2
Memory device related to a verify operation and method of operating the memory device
Jong Hoon Lee, Icheon-si (KR); and Se Chun Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 26, 2023, as Appl. No. 18/307,603.
Claims priority of application No. 10-2022-0156347 (KR), filed on Nov. 21, 2022.
Prior Publication US 2024/0170078 A1, May 23, 2024
Int. Cl. G11C 11/34 (2006.01); G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/3459 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/32 (2013.01); G11C 16/0483 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells programmed to a first program state through a plurality of program loops;
a page buffer configured to apply a program voltage to the plurality of memory cells, to perform a first verify operation of verifying the first program state based on a first evaluation time, and to perform a second verify operation of verifying the first program state based on a second evaluation time, in each of the plurality of program loops; and
control logic configured to, as the plurality of program loops are sequentially performed, adjust the first evaluation time so as to decrease the difference between the second evaluation time and the first evaluation time.