US 12,417,331 B2
Systems and methods for circuit design dependent programmable maximum junction temperatures
Archanna Srinivasan, San Jose, CA (US); Rajiv Mongia, Portland, OR (US); Ravi Gutala, San Jose, CA (US); Kaushik Chanda, San Jose, CA (US); Gurvinder Tiwana, Toronto (CA); Vadali Mahadev, San Jose, CA (US); and Mahesh A. Iyer, Fremont, CA (US)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 21, 2021, as Appl. No. 17/481,038.
Prior Publication US 2022/0004688 A1, Jan. 6, 2022
Int. Cl. G06F 30/337 (2020.01); G06F 30/343 (2020.01); G06F 119/08 (2020.01)
CPC G06F 30/337 (2020.01) [G06F 30/343 (2020.01); G06F 2119/08 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer readable storage medium comprising instructions stored thereon for causing a computer to execute a method for generating a circuit design for an integrated circuit using a circuit design tool, the method comprising:
placing and routing the circuit design to generate a placement and routing for the circuit design;
determining maximum junction temperatures and defects values for circuit blocks in the circuit design for the integrated circuit;
identifying hot spots in the placement and routing for the circuit design based on the maximum junction temperatures for the circuit blocks;
identifying portions of the circuit design that are larger contributors to the defects values based on the hot spots;
determining if there are changes to the placement and routing for the circuit design that reduce temperatures of the hot spots; and
performing the changes to the placement and routing for the circuit design to reduce the temperatures of the hot spots.