	US 12,417,076 B2
	Processing-in-memory (PIM) devices
Choung Ki Song, Yongin-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Oct. 12, 2021, as Appl. No. 17/499,331.
Application 17/499,331 is a continuation of application No. 17/410,752, filed on Aug. 24, 2021.
Application 17/410,752 is a continuation in part of application No. 17/090,462, filed on Nov. 5, 2020, granted, now 11,537,323.
Claims priority of provisional application 62/958,223, filed on Jan. 7, 2020.
Claims priority of application No. 10-2020-0006902 (KR), filed on Jan. 17, 2020.
Prior Publication US 2022/0027131 A1, Jan. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/544 (2006.01); G06F 7/523 (2006.01); G06F 17/16 (2006.01); G11C 7/10 (2006.01)

CPC G06F 7/5443 (2013.01) [G06F 7/523 (2013.01); G06F 17/16 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01)]

52 Claims

1. A processing-in-memory (PIM) device comprising:

first to L^thmultiplication/accumulation (MAC) operators configured to perform a MAC arithmetic operation for weight data of a weight matrix having “M”-number of rows (where, “L” is equal to “M/m”, “m” is a natural number, and “M” is a natural number which is equal to or greater than two), wherein the first to L^thMAC operators include first to L^thleft MAC operators generating respective ones of first to L^thleft MAC data and first to L^thright MAC operators generating respective ones of first to L^thright MAC data;

first to L^thmemory banks configured to provide the weight data to the first to L^thMAC operators, wherein the first to L^thmemory banks include first to L^thleft memory banks and first to L^thright memory banks;

first to L^thadditional adders configured to add the first to L^thleft MAC data generated by respective ones of the first to L^thleft MAC operators to the first to L^thright MAC data generated by respective ones of the first to L^thright MAC operators to generate and output first to Mth MAC result data; and

a plurality of data input/output (I/O) circuits including left data I/O circuits and right data I/O circuits configured to output the first to Mth MAC result data as output data of the PIM device,

wherein each of the first to L^thadditional adders is classified as either a left additional adder or a right additional adder,

wherein the left additional adders are configured to transmit a first portion of the first to M^thMAC result data to the left data I/O circuits, and

wherein the right additional adders are configured to transmit a second portion of the first to M^thMAC result data to the right data I/O circuits.