US 12,416,961 B2
Integrated circuit that mitigates inductive-induced voltage droop using compute unit group identifiers
Darshan Gandhi, Palo Alto, CA (US); Manish K. Shah, Austin, TX (US); Raghu Prabhakar, San Jose, CA (US); Gregory Frederick Grohoski, Bee Cave, TX (US); Youngmoon Choi, Milpitas, CA (US); and Jinuk Shin, San Jose, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Apr. 8, 2023, as Appl. No. 18/132,392.
Claims priority of provisional application 63/405,363, filed on Sep. 9, 2022.
Prior Publication US 2024/0094794 A1, Mar. 21, 2024
Int. Cl. G06F 1/3206 (2019.01); G06F 1/08 (2006.01)
CPC G06F 1/3206 (2013.01) [G06F 1/08 (2013.01)] 26 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
an array of compute units that are statically reconfigurable for separation into mutually exclusive groups, wherein each group includes no more than a statically reconfigurable number of compute units, wherein each compute unit comprises:
a register statically reconfigurable with a group identifier that identifies which group of the mutually exclusive groups the compute unit belongs to;
a counter, statically reconfigurable to synchronously increment with the counters of all the other compute units such that all the counters have the same value each clock cycle; and
control circuitry that prevents the compute unit from starting to process data until the counter value matches the group identifier;
wherein according to operation of the register, the counter, and the control circuitry, no more than the statically reconfigurable number of the compute units are allowed to start processing data concurrently to mitigate supply voltage droop caused by a time rate of change of current drawn by the IC through inductive loads of the IC.