US 12,416,867 B2
Overlay target and overlay method
Hui Liu, Singapore (SG)
Assigned to United Microelectronics Corp., Hsinchu (TW)
Filed by United Microelectronics Corp., Hsinchu (TW)
Filed on Oct. 7, 2022, as Appl. No. 17/961,575.
Claims priority of application No. 111135839 (TW), filed on Sep. 22, 2022.
Prior Publication US 2024/0103383 A1, Mar. 28, 2024
Int. Cl. G03F 7/00 (2006.01); H01L 23/544 (2006.01)
CPC G03F 7/70633 (2013.01) [H01L 23/544 (2013.01); H01L 2223/54426 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An overlay method, used to determine an overlay error of a device structure formed in a semiconductor manufacturing process, comprising:
forming a first overlay target, comprising:
providing a plurality of working zones;
forming a plurality of holes in a first sub-zone of each of the working zones; and
forming a first layer in the holes, wherein the holes are not filled up by the first layer, and a plurality of spaces are reserved, the spaces have a plurality of first diameters and a plurality of second diameters greater than the first diameters;
taking a plurality of midpoints of the second diameters of the spaces as a plurality of calibration center points;
forming a second overlay target, comprising forming a plurality of line segments in a second sub-zone of each of the working zones; and
determining the overlay error of the device structure by using the calibration center points and a plurality of centers of the line segments.