| CPC G02F 1/136286 (2013.01) [H10D 86/441 (2025.01); H10D 86/60 (2025.01)] | 11 Claims |
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1. A display panel having an active area and a peripheral area and comprising:
a substrate;
a plurality of pixels disposed on the substrate and in the active area;
a plurality of gate lines disposed on the substrate and configured to receive a plurality of scan signals, wherein each gate line is coupled to one or more of the pixels, wherein a number of pixels coupled to a first gate line of the gate lines is less than a number of pixels coupled to a second gate line of the gate lines, and wherein the first gate line crosses the active area and the peripheral area;
a gate connecting line in the peripheral area and electrically connected to the first gate line;
a common line in the peripheral area and disposed under the gate connecting line, the common line configured to receive a common voltage signal; and
a compensation electrode in the peripheral area and disposed over the gate connecting line, the compensation electrode configured to receive the common voltage signal;
wherein the common line, the gate connecting line and the compensation electrode are overlapped in a normal direction of the display panel.
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