US 12,416,093 B2
Electroless plating process
Chandrasekharan Nair, Mesa, AZ (US); Darko Grujicic, Chandler, AZ (US); Rengarajan Shanmugam, Chandler, AZ (US); Srinivasan Raman, Chandler, AZ (US); Roy Dittler, Chandler, AZ (US); Daniel Sowa, Casa Grande, AZ (US); Robert Baresel, II, Gilbert, AZ (US); Marcel Wall, Phoenix, AZ (US); and Rahul Manepalli, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2021, as Appl. No. 17/482,513.
Prior Publication US 2022/0010452 A1, Jan. 13, 2022
Int. Cl. C25D 17/06 (2006.01); C23C 18/16 (2006.01); C25D 17/00 (2006.01); C25D 17/12 (2006.01); H01L 21/67 (2006.01)
CPC C25D 17/06 (2013.01) [C23C 18/163 (2013.01); C23C 18/1642 (2013.01); C25D 17/008 (2013.01); C25D 17/12 (2013.01); H01L 21/6723 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An electroless plating process comprising:
providing a panel basket;
providing semiconductor panels comprising a plurality of metal pads;
providing a pretreatment etching for the semiconductor panels comprising:
placing the semiconductor panels into the panel basket made from a basket material;
shielding the metal pads on the semiconductor panel from contaminants during the pretreatment etching to prevent over-etching and under-etching of the metal pads on the semiconductor panels; and
performing electroless plating process steps with the semiconductor panels;
wherein the panel basket is configured with two panel end plates made of the basket material and a plurality of opposing slots for carrying the semiconductor panels in and out of baths during the electroless plating process;
wherein the semiconductor panels are positioned proximal to each of the panel end plates; and
wherein the shielding the metal pads comprises providing a distance between the contaminants and the metal pads by positioning an insulating insert between the semiconductor panels and the panel end plates.