US 12,416,074 B2
PVD system and collimator
Kuan-Lin Chen, New Taipei (TW); Tsung-Yi Chou, Changhua County (TW); Wei-Der Sun, Hsinchu (TW); and Hao-Wei Kang, Taoyuan County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 26, 2024, as Appl. No. 18/617,573.
Application 18/617,573 is a continuation of application No. 17/701,610, filed on Mar. 22, 2022, granted, now 11,952,656, issued on Apr. 9, 2024.
Claims priority of provisional application 63/235,652, filed on Aug. 20, 2021.
Prior Publication US 2024/0240306 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. C23C 14/35 (2006.01); C23C 14/50 (2006.01); H01J 37/34 (2006.01)
CPC C23C 14/354 (2013.01) [C23C 14/50 (2013.01); H01J 37/3441 (2013.01); H01J 37/3447 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A physical vapor deposition (PVD) system, comprising:
a pedestal configured to accommodate a semiconductor wafer;
a cover plate above the pedestal configured to hold a target; and
a collimator disposed above the pedestal and below the cover plate, wherein:
the collimator has an upper surface and a lower surface, the lower surface is flat, and the upper surface is non-flat, and
the collimator has a plurality of sidewall sheets defining a first plurality of passages in a peripheral portion of the collimator to each have a same width dimension between adjacent ones of the plurality of sidewall sheets and a same first vertical dimension, and defining a second plurality of passages in a central portion of the collimator to each have the same width dimension between adjacent ones of the plurality of sidewall sheets and a respective second vertical dimension, each respective second vertical dimension being smaller than the same first vertical dimension.