US 12,089,512 B2
Semiconductor structure
Shih-Wei Su, Tainan (TW); Da-Jun Lin, Kaohsiung (TW); Chih-Wei Chang, Tainan (TW); Bin-Siang Tsai, Changhua County (TW); and Ting-An Chien, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Sep. 6, 2023, as Appl. No. 18/242,550.
Application 18/242,550 is a division of application No. 17/114,438, filed on Dec. 7, 2020, granted, now 11,793,091.
Claims priority of application No. 202011221313.1 (CN), filed on Nov. 5, 2020.
Prior Publication US 2023/0413690 A1, Dec. 21, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01)
CPC H10N 70/063 (2023.02) [H10B 63/00 (2023.02); H10N 70/028 (2023.02); H10N 70/041 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a resistive random access memory (RRAM) located on the substrate, the resistive random access memory comprises an upper electrode, a lower electrode and a resistance conversion layer located between the upper electrode and the lower electrode; and
a cap layer covering an outside of the resistance random access memory, wherein the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.