US 12,089,445 B2
Array substrate having via hole connecting conductive portions, fabrication method thereof and display device
Yipeng Chen, Beijing (CN); Ling Shi, Beijing (CN); and Wenqiang Li, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/438,445
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Chengdu (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Oct. 27, 2020, PCT No. PCT/CN2020/124165
§ 371(c)(1), (2) Date Sep. 12, 2021,
PCT Pub. No. WO2022/087852, PCT Pub. Date May 5, 2022.
Prior Publication US 2022/0310732 A1, Sep. 29, 2022
Int. Cl. H10K 59/121 (2023.01); H10K 59/131 (2023.01); H10K 59/12 (2023.01)
CPC H10K 59/1213 (2023.02) [H10K 59/1216 (2023.02); H10K 59/131 (2023.02); H10K 59/1201 (2023.02)] 19 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a pixel driving circuit, the pixel driving circuit comprising a P-type driving transistor, an N-type first transistor, and a capacitor, wherein a first electrode of the N-type first transistor is connected to a gate electrode of the P-type driving transistor, and a first electrode of the capacitor is connected to the gate electrode of the P-type driving transistor;
a base substrate;
a first conductive layer laminated at a side of the base substrate, the first conductive layer comprising a first conductive portion, and the first conductive portion being configured as the gate electrode of the P-type driving transistor and the first electrode of the capacitor;
a first dielectric layer laminated at a side of the first conductive layer facing away from the base substrate;
a first buffer layer laminated at a side of the first dielectric layer facing away from the base substrate, a slot being provided on the first buffer layer, and an orthographic projection of the slot on the base substrate being at least partially overlapped with an orthographic projection of the first conductive portion on the base substrate; and
a second conductive layer laminated at a side of the first buffer layer facing away from the base substrate, the second conductive layer comprising:
a second conductive portion configured as a gate electrode of the N-type first transistor; and
a third conductive portion at least partially at a bottom portion of the slot, an orthographic projection of the third conductive portion on the base substrate being at least partially overlapped with the orthographic projection of the first conductive portion on the base substrate, so as to form a second electrode of the capacitor.