| CPC H10B 61/22 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a substrate that includes a first region and a second region;
a first lower conductive pattern on the first region of the substrate;
a second lower conductive pattern on the second region of the substrate;
a plurality of upper conductive patterns on the first lower conductive pattern and the second lower conductive pattern;
a memory cell on the first region of the substrate and serially connecting the first lower conductive pattern to one of the upper conductive patterns, the memory cell including a bottom electrode, a magnetic tunnel junction, and a top electrode; and
a through electrode on the second region of the substrate and connecting the second lower conductive pattern to another of the upper conductive patterns,
wherein:
a top surface of the first lower conductive pattern is at a level lower than a level of a top surface of the second lower conductive pattern, and
the bottom electrode has a lateral surface, a top surface in contact with the magnetic tunnel junction, and a connection surface between the lateral surface and the top surface, the connection surface being inclined relative to the lateral surface.
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