US 12,089,417 B2
Semiconductor memory devices and methods of manufacturing thereof
Chia-En Huang, Xinfeng (TW); and Meng-Han Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 27, 2021, as Appl. No. 17/459,847.
Claims priority of provisional application 63/172,169, filed on Apr. 8, 2021.
Prior Publication US 2022/0328524 A1, Oct. 13, 2022
Int. Cl. H10B 51/50 (2023.01); H01L 23/522 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/50 (2023.02) [H01L 23/5226 (2013.01); H10B 51/20 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating memory devices, comprising:
providing a substrate including a first area and a second area;
forming a plurality of first transistors in the first area and a plurality of second transistors in the second area;
forming a stack over the second area, wherein the stack comprises a plurality of insulating layers and a plurality of sacrificial layers alternatively stacked on top of each other;
forming a memory array portion and an interface portion through the stack, wherein the memory array portion includes a plurality of memory strings and the interface portion includes a plurality of first conductive structures extending along a lateral direction; and
simultaneously forming a plurality of second conductive structures in the first area and forming a plurality of third conductive structures in the second area, wherein the second conductive structures each vertically extends to electrically couple to at least one of the first transistors, and the third conductive structures each vertically extends through one of the plurality of memory strings to electrically couple to at least one of the second transistors.