US 12,089,413 B2
Peripheral circuit having recess gate transistors and method for forming the same
Yanwei Shi, Wuhan (CN); Yanhong Wang, Wuhan (CN); Cheng Gan, Wuhan (CN); Liang Chen, Wuhan (CN); Wei Liu, Wuhan (CN); Zhiliang Xia, Wuhan (CN); Wenxi Zhou, Wuhan (CN); Kun Zhang, Wuhan (CN); and Yuancheng Yang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Oct. 26, 2021, as Appl. No. 17/510,752.
Application 17/510,752 is a continuation of application No. PCT/CN2021/103603, filed on Jun. 30, 2021.
Prior Publication US 2023/0005946 A1, Jan. 5, 2023
Int. Cl. H10B 43/40 (2023.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/41 (2023.01)
CPC H10B 43/40 (2023.02) [G11C 16/0483 (2013.01); G11C 16/24 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/41 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
an array of memory cells; and
a plurality of peripheral circuits coupled to the array of memory cells, wherein the peripheral circuits comprise a first peripheral circuit comprising a recess gate transistor, and a second peripheral circuit comprising a flat gate transistor,
wherein:
the recess gate transistor comprises a gate electrode that protrudes into a substrate; and
a gate length of the gate electrode protruding into the substrate decreases with an increase of a depth of the gate electrode into the substrate, and a bottom of the gate electrode comprises a flat surface.