US 12,089,410 B2
Semiconductor memory device and method for manufacturing the same
Yoshiaki Fukuzumi, Yokkaichi (JP); Shinya Arai, Yokkaichi (JP); Masaki Tsuji, Yokkaichi (JP); Hideaki Aochi, Yokkaichi (JP); and Hiroyasu Tanaka, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jul. 7, 2023, as Appl. No. 18/348,418.
Application 18/348,418 is a continuation of application No. 17/672,819, filed on Feb. 16, 2022, granted, now 11,744,075.
Application 17/672,819 is a continuation of application No. 17/335,214, filed on Jun. 1, 2021, granted, now 11,296,114, issued on Apr. 5, 2022.
Application 17/335,214 is a continuation of application No. 16/918,005, filed on Jul. 1, 2020, granted, now 11,063,064, issued on Jul. 13, 2021.
Application 16/918,005 is a continuation of application No. 16/596,892, filed on Oct. 9, 2019, granted, now 10,741,583, issued on Aug. 11, 2020.
Application 16/596,892 is a continuation of application No. 16/138,619, filed on Sep. 21, 2018, granted, now 10,497,717, issued on Dec. 3, 2019.
Application 16/138,619 is a continuation of application No. 15/345,790, filed on Nov. 8, 2016, granted, now 10,115,733, issued on Oct. 30, 2018.
Application 15/345,790 is a continuation of application No. 14/614,588, filed on Feb. 5, 2015, granted, now 9,520,407, issued on Dec. 13, 2016.
Claims priority of application No. 2014-021747 (JP), filed on Feb. 6, 2014.
Prior Publication US 2023/0363167 A1, Nov. 9, 2023
Int. Cl. H10B 43/27 (2023.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H10B 43/10 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 29/42344 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01); H10B 43/10 (2023.02); H10B 43/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device comprising:
a semiconductor substrate;
an insulating layer provided above the semiconductor substrate;
a first conductive layer functioning a source layer provided above the insulating layer;
electrode films stacked above the first conductive layer in a first direction perpendicular to a surface of the semiconductor substrate to constitute a stacked body;
semiconductor bodies piercing through the electrode films in the first direction, lower ends of the semiconductor bodies being electrically connected to the first conductive layer, the semiconductor bodies forming memory cells at crossing portions with a part of the electrode films;
a first isolating portion provided in a first slit portion extending in the first direction and in a second direction perpendicular to the first direction along one side of the stacked body in a third direction perpendicular to the first direction and the second direction;
a second isolating portion provided in a second slit portion extending in the first and second directions along the other side of the stacked body in the third direction; and
a third isolating portion provided in a third slit portion extending in the first and third directions, one end of the third slit portion in the third direction being coupled to one end of the first slit portion in the second direction and the other end of the third slit portion in the third direction being coupled to one end of the second slit portion in the second direction, and the third isolating portion being in contact with an end of the stacked body in the second direction.