US 12,089,409 B2
Semiconductor memory
Masayoshi Tagami, Kuwana (JP); Jun Iijima, Yokkaichi (JP); Ryota Katsumata, Yokkaichi (JP); and Kazuyuki Higashi, Yokohama (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jun. 22, 2023, as Appl. No. 18/339,526.
Application 18/339,526 is a continuation of application No. 17/160,563, filed on Jan. 28, 2021, granted, now 11,729,973.
Application 17/160,563 is a continuation of application No. 16/927,309, filed on Jul. 13, 2020, granted, now 10,950,630, issued on Mar. 16, 2021.
Application 16/927,309 is a continuation of application No. 16/707,646, filed on Dec. 9, 2019, granted, now 10,748,928, issued on Aug. 18, 2020.
Application 16/707,646 is a continuation of application No. 16/460,410, filed on Jul. 2, 2019, granted, now 10,553,612, issued on Feb. 4, 2020.
Application 16/460,410 is a continuation of application No. 15/911,369, filed on Mar. 5, 2018, granted, now 10,381,374, issued on Aug. 13, 2019.
Claims priority of application No. 2017-179348 (JP), filed on Sep. 19, 2017.
Prior Publication US 2023/0345726 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); G11C 5/02 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H01L 24/04 (2013.01); H01L 25/0657 (2013.01); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); G11C 5/02 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 2224/05095 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/80201 (2013.01); H01L 2224/80894 (2013.01); H01L 2224/80895 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1434 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor memory comprising:
a memory chip comprising a first area, a second area, and a third area provided in this order in a first direction,
the first area comprising a first memory cell array that comprises first memory cells, a first bit line, and a first word line,
the second area not comprising a memory cell array,
the third area comprising a second memory cell array that comprises second memory cells, a second bit line, and a second word line; and
a circuit chip attached to the memory chip and comprising a fourth area, a fifth area, and a sixth area provided in this order in the first direction,
the fourth area comprising a first sense amplifier electrically connected to one of the first memory cells via the first bit line,
the fifth area not comprising a sense amplifier,
the sixth area comprising a second sense amplifier electrically connected to one of the second memory cells via the second bit line;
wherein the first area and the fourth area overlap in a second direction crossing the first direction, and
the third area and the sixth area overlap in the second direction.