US 12,089,408 B2
Non-volatile memory device including common source line tapping wire connected to common source line plate by vias on lower metal line and through-hole vias
Bongsoon Lim, Seoul (KR); and Hyunggon Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 17, 2022, as Appl. No. 17/697,386.
Claims priority of application No. 10-2021-0092379 (KR), filed on Jul. 14, 2021.
Prior Publication US 2023/0027955 A1, Jan. 26, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 16/06 (2006.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 16/0483 (2013.01); G11C 16/06 (2013.01); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device comprising:
a memory cell region including an upper substrate, channel structures, and a first upper metal line, the channel structure extending in a vertical direction on the upper substrate, the first upper metal line extending in a first horizontal direction above the channel structures; and
a peripheral circuit region below the memory cell region in the vertical direction, the peripheral circuit region including a first lower metal line extending in a second horizontal direction, a first via structure on the first lower metal line, and a second via structure on the first lower metal line, a top surface of the second via structure being in contact with the upper substrate,
wherein the memory cell region further includes a first through-hole via structure, the first through-hole via structure extending in the vertical direction, the first through-hole via structure passing through the upper substrate and the first via structure, and the first through-hole via structure electrically connecting the first upper metal line to the first lower metal line, and
wherein the first upper metal line is electrically connected to the upper substrate through the first through-hole via structure, the first lower metal line, and the second via structure.