US 12,089,404 B2
Semiconductor memory device including a substrate, various interconnections, semiconductor member, charge storage member and a conductive member
Yoshiro Shimojo, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 2, 2021, as Appl. No. 17/165,169.
Application 17/165,169 is a continuation of application No. 15/931,961, filed on May 14, 2020, granted, now 10,943,914.
Application 15/931,961 is a continuation of application No. 15/929,080, filed on Jan. 2, 2019, granted, now 10,672,779, issued on Jun. 2, 2020.
Application 15/929,080 is a continuation of application No. 15/934,437, filed on Mar. 23, 2018, granted, now 10,217,757, issued on Feb. 26, 2019.
Application 15/934,437 is a continuation of application No. 15/455,443, filed on Mar. 10, 2017, granted, now 9,960,173, issued on May 1, 2018.
Claims priority of application No. 2016-047644 (JP), filed on Mar. 10, 2016.
Prior Publication US 2021/0159237 A1, May 27, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 41/50 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01)
CPC H10B 41/50 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02)] 24 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a substrate;
a peripheral circuit on the substrate;
a first wiring provided above the peripheral circuit;
a first pillar extending in a first direction perpendicular to a surface of the substrate, the first pillar including a first semiconductor member, the first wiring being provided between the first pillar and the peripheral circuit in the first direction and electrically connected to the first semiconductor member;
a second pillar extending in the first direction, the second pillar including a second semiconductor member, the first wiring being provided between the second pillar and the peripheral circuit in the first direction and electrically connected to the second semiconductor member;
a first conductive member extending in the first direction, the first conductive member being provided between the first pillar and the second pillar in a second direction perpendicular to the first direction and electrically connected to the peripheral circuit;
a second conductive member extending in the first direction, the second conductive member being provided between the first pillar and the second pillar in the second direction and electrically connected to the peripheral circuit;
a plurality of conductive layers arranged to be separated from each other along the first direction above the first wiring, the plurality of conductive layers including a first conductive layer;
a first insulating member provided between the first conductive member and the first conductive layer and surrounding the first conductive member;
a second insulating member provided between the second conductive member and the first conductive layer and surrounding the second conductive member;
a third pillar extending in the first direction, the first wiring being provided between the third pillar and the peripheral circuit in the first direction; and
a fourth pillar extending in the first direction, the first wiring being provided between the fourth pillar and the peripheral circuit in the first direction, the first conductive member being provided between the third pillar and the fourth pillar in a third direction perpendicular to the first direction and the second direction.