CPC H10B 41/27 (2023.02) [H01L 21/31144 (2013.01); H10B 41/10 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] | 14 Claims |
1. A memory array, comprising:
laterally-spaced memory blocks, wherein each of the laterally-spaced memory blocks comprises sub-blocks that are defined at least in part by channel openings and laterally-spaced upper select gates and lower select gates on each of the laterally-spaced memory blocks;
an isolation structure that laterally separates immediately adjacent sub-blocks which are defined at least by the laterally-spaced upper select gates;
a dummy channel-material string that extends elevationally above the lower select gates and through the isolation structure;
a vertical stack below the upper select gates having alternating insulative tiers and wordline tiers; and
channel-material strings extending elevationally through the upper select gates and through the insulative tiers and the wordline tiers within the sub-blocks, the channel-material strings having a common horizontal pitch-spacing within individual of the sub-blocks along parallel horizontally-straight lines between longitudinal edges of the individual laterally-spaced memory blocks, the channel-material strings along the parallel horizontally-straight lines being horizontally spaced from one another by the isolation structure between the immediately-adjacent sub-blocks by a distance that is greater than the common horizontal pitch-spacing.
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