US 12,088,947 B2
Methods and apparatus for a track and hold amplifier
Shankar Ramakrishnan, Bangalore (IN)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Apr. 3, 2023, as Appl. No. 18/194,756.
Application 18/194,756 is a continuation of application No. 16/444,995, filed on Jun. 18, 2019, granted, now 11,647,312.
Application 16/444,995 is a continuation of application No. 15/666,781, filed on Aug. 2, 2017, granted, now 10,375,336, issued on Aug. 6, 2019.
Prior Publication US 2023/0254606 A1, Aug. 10, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 25/778 (2023.01); G11C 27/02 (2006.01); H03F 1/22 (2006.01); H03F 1/34 (2006.01); H03F 3/72 (2006.01); H03G 1/00 (2006.01); H03K 5/08 (2006.01); H03M 1/12 (2006.01); H04N 25/75 (2023.01); H04N 25/772 (2023.01)
CPC H04N 25/778 (2023.01) [G11C 27/026 (2013.01); H03F 1/223 (2013.01); H03F 1/34 (2013.01); H03F 3/72 (2013.01); H03G 1/0094 (2013.01); H03K 5/08 (2013.01); H04N 25/75 (2023.01); H04N 25/772 (2023.01); H03F 2203/7221 (2013.01); H03M 1/1245 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A track-and-hold amplifier circuit, comprising:
a gain setting circuit configured to receive an input signal;
a cascode circuit connected to the gain setting circuit;
a capacitor comprising first and second capacitor terminals, wherein the first capacitor terminal is connected to an output node and wherein the output node is selectively connected to the cascode circuit; and
an isolation circuit connected to the second capacitor terminal, the cascode circuit, and a ground node.