CPC H04L 5/0048 (2013.01) [H04W 48/08 (2013.01)] | 26 Claims |
1. An apparatus for wireless communication at a base station, comprising:
one or more memories; and
one or more processors coupled to the one or more memories and configured, individually or collectively, to:
schedule a plurality of synchronization signal blocks (SSBs) in an extended discovery burst (DRS) transmission window comprising a plurality of candidate SSBs including at least two candidate SSBs with a same SSB beam index; and
transmit the plurality of SSBs based on the scheduling of the plurality of SSBs in the extended DRS transmission window, wherein the plurality of SSBs comprises a pattern of SSBs, and wherein the base station sequentially repeats transmission of each SSB of the pattern of SSBs N times, N being an integer number greater than or equal to 2, and wherein a first SSB and a repetition of the first SSB are transmitted prior to transmitting a second SSB within the extended DRS transmission window.
|