US 12,088,429 B2
Microcontroller circuit, corresponding device, system and method of operation
Fred Rennig, Nandlstadt (DE); and Vaclav Dvorak, Mratín (CZ)
Assigned to STMicroelectronics Design and Application S.R.O., Prague (CZ); and STMicroelectronics Application GmbH, Aschheim-Dornach (DE)
Filed by STMicroelectronics Design and Application S.R.O., Prague (CZ); and STMicroelectronics Application GMBH, Aschheim-Dornach (DE)
Filed on Feb. 22, 2022, as Appl. No. 17/677,113.
Claims priority of application No. 102021000005354 (IT), filed on Mar. 8, 2021.
Prior Publication US 2022/0286319 A1, Sep. 8, 2022
Int. Cl. H04L 12/403 (2006.01); H03K 7/08 (2006.01); H04L 12/40 (2006.01)
CPC H04L 12/403 (2013.01) [H03K 7/08 (2013.01); H04L 12/40006 (2013.01); H04L 2012/40215 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first memory and a second memory;
a processor coupled to the first memory and the second memory, the processor configured to:
generate an output sequence comprising binary values encoding an outgoing Controller Area Network (CAN) frame according to a CAN protocol,
process the output sequence to detect a sequence of ordered pulse-width modulated (PWM) periods, each PWM period comprising a first portion having a dominant state and a second portion having a recessive state, each PWM period having a respective total duration and a respective duty-cycle value, wherein the processing the output sequence comprises:
detecting a start-of-frame bit having a dominant value in the output sequence;
counting a first number of consecutive bits having a dominant value in the output sequence until detecting a first bit having a recessive value;
counting a second number of consecutive bits having a recessive value in the output sequence until detecting a first bit having a dominant value; and
repeating the counting the first number and the counting the second number until having detected and processed an end-of-frame field in the output sequence,
store a set of ordered first values indicative of a first parameter of the PWM periods in the sequence of ordered PWM periods in the first memory, and
store a set of ordered second values indicative of a second parameter of the PWM periods in the sequence of ordered PWM periods in the second memory, wherein the first parameter and the second parameter define a shape of the PWM periods; and
a timer circuit comprising:
a first register configured to read from the first memory and store a value indicative of the first parameter of a current PWM period in the sequence of ordered PWM periods;
a counter circuit configured to:
increase an internal count number and reset the internal count number as a function of the value stored in the first register,
trigger reading from the first memory, and
trigger storing into the first register a subsequent value indicative of the first parameter of a subsequent PWM period in the sequence of ordered PWM periods as a function of the value stored in the first register; and
a second register configured to:
read from the second memory and store a value indicative of the second parameter of the current PWM period,
compare the internal count number of the counter circuit to the value stored into the second register,
drive an output pin of the circuit to a dominant value or to a recessive value as a function of the comparing the internal count number of the counter circuit to the value stored into the second register, the output pin providing an output PWM signal comprising the sequence of ordered PWM periods,
read from the second memory, and
store a subsequent value indicative of the second parameter of a subsequent PWM period in the sequence of ordered PWM periods in response to the internal count number of the counter circuit reaching the value stored into the second register or in response to the internal count number of the counter circuit reaching the value stored into the first register.