CPC H04L 1/1822 (2013.01) [H04L 1/0003 (2013.01); H04L 1/0026 (2013.01); H04L 1/0048 (2013.01); H04L 1/1819 (2013.01); H04W 4/40 (2018.02)] | 20 Claims |
1. A system, comprising:
a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
decoding a data packet received from a network node device of a network;
in response to the decoding of the data packet, estimating a decoding quality associated with a potential modulation and coding scheme value that is greater than a current data packet value; and
in response to a value representative of the decoding quality being determined to be less than a threshold value, transmitting acknowledgement plus data indicative of a quality lapse between the decoding quality and a channel quality of the network.
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