CPC H04L 1/0061 (2013.01) [H04L 1/0079 (2013.01)] | 20 Claims |
1. Cyclic Redundancy Check value calculation circuitry comprising:
a demultiplexer that receives an input data bit stream and outputs a plurality of split data bit streams based on the input data bit stream, wherein each split data bit stream in the plurality of split data bit streams includes one or more inserted bits;
a plurality of Cyclic Redundancy Check value generators that each generate a partial Cyclic Redundancy Check value based on a corresponding split data bit stream in the plurality of split data bit streams;
logic circuitry coupled to each Cyclic Redundancy Check value generator in the plurality of Cyclic Redundancy Check value generators and that generates a final Cyclic Redundancy Check value based on the partial Cyclic Redundancy Check values; and
a Cyclic Redundancy Check value data storage structure that stores a plurality of pre-computed Cyclic Redundancy Check values accessible by each Cyclic Redundancy Check value generator in the plurality of Cyclic Redundancy Check value generators.
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