CPC H04B 7/212 (2013.01) [H04B 1/16 (2013.01)] | 20 Claims |
19. A system, comprising:
a computer that comprises a first processor and a memory, the memory comprising instructions executable by the first processor to:
determine burst time plans (BTPs);
receive burst mode time division multiple access (TDMA) data;
distribute the burst mode TDMA data among second processors based on the BTPs by sorting the BTPs in descending order based on packet sizes and distributing the burst mode TDMA data to channel groups in round robin fashion in the sorted order, and then distribute the burst mode TDMA data in each channel group to one of the second processors based on the sorted BTPs;
demodulate and decode the burst mode TDMA data using the second processors; and
output the demodulated and decoded burst mode TDMA data.
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