US 12,088,324 B2
Excess loop delay compensation for a delta-sigma modulator
Ahmed Abdelaal, Ulm (DE); John G. Kauffman, Neu-Ulm (DE); Maurits Ortmanns, Ulm (DE); and Takashi Miki, Neu-Ulm (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Aug. 19, 2022, as Appl. No. 17/820,975.
Prior Publication US 2024/0063812 A1, Feb. 22, 2024
Int. Cl. H03M 3/00 (2006.01)
CPC H03M 3/344 (2013.01) [H03M 3/372 (2013.01); H03M 3/422 (2013.01); H03M 3/436 (2013.01); H03M 3/464 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A delta-sigma modulator comprising:
an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion;
a quantizer coupled to an output of the inner portion of the analog loop filter;
an outer feedback path coupled between an output of the quantizer and an input of the outer portion of the analog loop filter; and
a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter, wherein:
the compensation filter has a transfer function configured to correct for an effect of an outer excess loop delay (ELD) and an inner ELD on the delta-sigma modulator,
the outer ELD comprises a delay from the input of the quantizer to the input of the outer portion of the analog loop filter including the outer feedback path, and the inner ELD comprises a delay from the input to the quantizer to the input of the inner portion of the analog loop filter including at least a portion of the outer feedback path,
the inner ELD is less than one clock cycle of the delta-sigma modulator, and
the outer ELD is at least two clock cycles of the delta-sigma modulator.