CPC H03M 13/19 (2013.01) [H03M 13/159 (2013.01); H03M 13/617 (2013.01)] | 14 Claims |
1. A memory system comprising:
a plurality of memory components; and
a controller in communication with the plurality of memory components and configured to:
store at least one codeword read from the plurality of memory components as beats of data organized to form a memory transfer block (MTB); and
perform error correction code (ECC) operations on the beats of data within the MTB:
wherein the ECC operations include performing (i) encoding the MTB data as a function of a data vector within each of the beats and a parity check matrix and (ii) decoding including computing a syndrome of the encoded MTB data and decoding corresponding Bose-Chaudhuri-Hocquenghem (BCH) codes; and
wherein the performing of the encoding and decoding include vector matrix multiplication.
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