US 12,088,322 B2
Method and system for on-ASIC error control decoding
Marco Sforzin, Boise, ID (US); and Paolo Amato, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 24, 2022, as Appl. No. 17/894,777.
Claims priority of provisional application 63/301,020, filed on Jan. 19, 2022.
Prior Publication US 2023/0231578 A1, Jul. 20, 2023
Int. Cl. H03M 13/19 (2006.01); H03M 13/00 (2006.01); H03M 13/15 (2006.01)
CPC H03M 13/19 (2013.01) [H03M 13/159 (2013.01); H03M 13/617 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory system comprising:
a plurality of memory components; and
a controller in communication with the plurality of memory components and configured to:
store at least one codeword read from the plurality of memory components as beats of data organized to form a memory transfer block (MTB); and
perform error correction code (ECC) operations on the beats of data within the MTB:
wherein the ECC operations include performing (i) encoding the MTB data as a function of a data vector within each of the beats and a parity check matrix and (ii) decoding including computing a syndrome of the encoded MTB data and decoding corresponding Bose-Chaudhuri-Hocquenghem (BCH) codes; and
wherein the performing of the encoding and decoding include vector matrix multiplication.