CPC H03K 5/01 (2013.01) [G06F 1/06 (2013.01); H03K 2005/00019 (2013.01); H03K 2005/00286 (2013.01)] | 30 Claims |
1. A clock generation apparatus comprising:
a delay circuit configured to output a first signal that is a delayed version of an input signal;
a phase selection circuit configured to receive the input signal and one or more phase-shifted versions of the input signal and to output a second signal that is a phase-shifted version of the input signal; and
a phase measurement circuit coupled to the first signal and the second signal, the phase measurement circuit providing a first output that is coupled to a phase control input of the phase selection circuit, the phase measurement circuit further providing a second output that is coupled to a delay control input of the delay circuit.
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