US 12,088,296 B2
Clock gating using a cascaded clock gating control signal
Ramon A. Mangaser, Boxborough, MA (US); Srikanth Reddy Gruddanti, Bangalore (IN); Prasant Kumar Vallur, Bangalore (IN); Krishna Reddy Mudimela Venkata, Bangalore (IN); and Oikwan Tsang, Santa Clara, CA (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Dec. 17, 2021, as Appl. No. 17/554,722.
Prior Publication US 2023/0198527 A1, Jun. 22, 2023
Int. Cl. H03K 19/20 (2006.01); G06F 1/06 (2006.01); H03K 3/037 (2006.01)
CPC H03K 19/20 (2013.01) [G06F 1/06 (2013.01); H03K 3/037 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock circuit for clock gating using a cascaded clock gating control signal, comprising:
a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal of a multiphase clock;
a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal of the multiphase clock instead of the first clock signal of the multiphase clock, wherein the output from the first B-latch varies based on the first clock signal to one of a value latched by the first B-latch or the input of the first B-latch and an output from the second B-latch varies based on the second clock signal to either a value latched by the second B-latch or the input of the second B-latch:
a first logic outputting, based on the first B-latch, a first gated clock signal; and
a second logic outputting, based on the second B-latch, a second gated clock signal.