US 12,088,291 B2
Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device
Changkyo Lee, Suwon-si (KR); Dongkeon Lee, Suwon-si (KR); Jinhoon Jang, Suwon-si (KR); Kyungsoo Ha, Suwon-si (KR); Kiseok Oh, Suwon-si (KR); and Kyungryun Kim, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 26, 2023, as Appl. No. 18/372,726.
Application 18/372,726 is a continuation of application No. 17/987,032, filed on Nov. 15, 2022, granted, now 11,799,479.
Application 17/987,032 is a continuation of application No. 17/974,873, filed on Oct. 27, 2022, granted, now 11,799,478.
Application 17/974,873 is a continuation of application No. 17/577,141, filed on Jan. 17, 2022, granted, now 11,664,803, issued on May 30, 2023.
Application 17/577,141 is a continuation of application No. 17/024,229, filed on Sep. 17, 2020, granted, now 11,245,397, issued on Feb. 8, 2022.
Application 17/024,229 is a continuation of application No. 16/552,147, filed on Aug. 27, 2019, granted, now 10,797,700, issued on Oct. 6, 2020.
Claims priority of application No. 10-2018-0167576 (KR), filed on Dec. 21, 2018; and application No. 10-2019-0049826 (KR), filed on Apr. 29, 2019.
Prior Publication US 2024/0014817 A1, Jan. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/00 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); H03K 19/0175 (2006.01); H03K 19/018 (2006.01)
CPC H03K 19/0005 (2013.01) [G06F 3/0604 (2013.01); G06F 3/061 (2013.01); G11C 7/1051 (2013.01); G11C 7/1084 (2013.01); H03K 19/017545 (2013.01); H03K 19/01825 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first on-die termination circuit connected to a data pin for transmitting or receiving a data signal and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the data pin;
a second on-die termination circuit connected to a read data strobe pin for transmitting or receiving a read data strobe signal and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the read data strobe pin; and
an on-die termination control circuit configured to independently control an enable timing and a disable timing of the first on-die termination circuit and an enable timing and a disable timing of the second on-die termination circuit,
wherein in response to the memory device receiving a read command from a memory controller at a first time point, the on-die termination control circuit is configured to control the second on-die termination circuit in an enable state to be disabled after a first time period from the first time point, control the first on-die termination circuit in an enable state to be disabled after a second time period from the first time point, control the first on-die termination circuit in the disable state to be enabled after a third time period from the first time point, and control the second on-die termination circuit in the disable state to be enabled after a fourth time period from the first time point, and
wherein the first time period is shorter than the second time period, the second time period is shorter than the third time period, and the third time period is shorter than the fourth time period.