US 12,088,284 B2
Discrete relay driver circuit for peak and hold operation
Karthik Naik, Jalan Eunos (SG); Wong Chuan Ming, Tressure Crest (SG); Venkata Jaya Sai Praneeth Ammanamanchi, Lamadelaine (LU); and Engel Joseph, Oberkorn (LU)
Assigned to DELPHI TECHNOLOGIES IP LIMITED, Saint Michael (BB)
Filed by Delphi Technologies IP Limited, St. Michael (BB)
Filed on Feb. 14, 2023, as Appl. No. 18/109,402.
Prior Publication US 2024/0275372 A1, Aug. 15, 2024
Int. Cl. H03K 17/06 (2006.01); H03K 17/0412 (2006.01); H03K 17/16 (2006.01)
CPC H03K 17/063 (2013.01) [H03K 17/04123 (2013.01); H03K 17/165 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A discrete relay driver circuit comprising:
a first high side gate drive circuit configured to drive a first high side metal-oxide-semiconductor field-effect transistor (MOSFET) based on a first voltage enable signal;
a second high side gate drive circuit configured to drive a second high side MOSFET based on a second voltage enable signal;
a first resistor divider configured to sense voltage from the first high side MOSFET;
a second resistor divider configured to sense voltage from the second high side MOSFET;
a first low side gate driver circuit configured to drive a first low side MOSFET based on a power factor correction enable signal;
a second low side gate driver circuit configured to drive a second low side MOSFET based on a first low side enable signal; and
a third low side gate driver circuit configured to drive a third low side MOSFET based on a second low side enable signal.