US 12,088,085 B2
Overvoltage protection circuit for a PMOS based switch
Manoj Kumar, Greater Noida (IN); Ravinder Kumar, Ambala (IN); and Nicolas Demange, Saint-Maximin la Sainte Baume (FR)
Assigned to STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR); and STMicroelectronics International N.V., Geneva (CH)
Filed by STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR); and STMicroelectronics International N.V., Geneva (CH)
Filed on Jan. 20, 2023, as Appl. No. 18/157,737.
Application 18/157,737 is a continuation of application No. 17/095,652, filed on Nov. 11, 2020, granted, now 11,575,254.
Claims priority of provisional application 62/937,720, filed on Nov. 19, 2019.
Prior Publication US 2023/0155369 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H02H 3/20 (2006.01); H02H 1/00 (2006.01)
CPC H02H 3/20 (2013.01) [H02H 1/0007 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A device, comprising:
a voltage generator that includes:
a first transistor that includes a gate coupled to a pad voltage, a first terminal coupled to a supply voltage, and a second terminal;
a second transistor that includes a gate coupled to the supply voltage, a first terminal to the pad voltage, and a second terminal coupled to the second terminal of the first transistor at a first node;
a third transistor that includes a gate coupled to the first node, a first terminal coupled to the first node, and a second terminal coupled to the supply voltage.