US 12,087,868 B2
Epitaxial wafer, method of manufacturing the epitaxial wafer, diode, and current rectifier
Richard Notzel, Guangzhou (CN)
Assigned to SOUTH CHINA NORMAL UNIVERSITY, Guangdong (CN)
Appl. No. 17/629,343
Filed by SOUTH CHINA NORMAL UNIVERSITY, Guangdong (CN)
PCT Filed Sep. 11, 2019, PCT No. PCT/CN2019/105398
§ 371(c)(1), (2) Date Jan. 21, 2022,
PCT Pub. No. WO2021/042407, PCT Pub. Date Mar. 11, 2021.
Claims priority of application No. 201910849997.0 (CN), filed on Sep. 2, 2019.
Prior Publication US 2022/0254939 A1, Aug. 11, 2022
Int. Cl. H01L 29/885 (2006.01); H01L 21/02 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H02M 7/06 (2006.01)
CPC H01L 29/885 (2013.01) [H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/02488 (2013.01); H01L 21/0254 (2013.01); H01L 21/02631 (2013.01); H01L 29/2003 (2013.01); H01L 29/66204 (2013.01); H02M 7/06 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An epitaxial wafer comprising:
a Si substrate layer;
an insulating layer formed on the Si substrate layer; and
a nitride semiconductor layer formed on a surface of the insulating layer facing away from the Si substrate layer,
wherein the insulating layer is configured to have a thickness allowing free electrons to pass through the insulating layer via quantum tunneling,
wherein the nitride semiconductor layer is an InGaN layer made by mixing GaN with InN,
wherein an In content in the InGaN layer is between 30% and 80%,
wherein a conduction band of the InGaN layer is aligned with a valence band of the Si substrate layer.