US 12,087,853 B2
Semiconductor device, method of fabricating the same, and display device including the same
Jinjoo Park, Yongin-si (KR); Junhee Choi, Seongnam-si (KR); Kiho Kong, Suwon-si (KR); Joohun Han, Hwaseong-si (KR); Nakhyun Kim, Yongin-si (KR); and Junghun Park, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 7, 2022, as Appl. No. 17/982,164.
Application 17/982,164 is a division of application No. 16/826,926, filed on Mar. 23, 2020, granted, now 11,527,642.
Claims priority of application No. 10-2019-0124776 (KR), filed on Oct. 8, 2019.
Prior Publication US 2023/0062456 A1, Mar. 2, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 27/15 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 27/1214 (2013.01); H01L 27/156 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01); H01L 27/15 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
stacking a lower semiconductor layer, an active layer, an upper semiconductor layer, a separation layer, an etch-stop layer, a channel layer, and a channel supply layer on an upper region of a substrate which includes a first region and a second region adjacent to the first region, the first region and the second region being disposed in a first direction parallel to an upper surface of the substrate;
etching a portion of the channel supply layer, a portion of the channel layer, and a portion of the separation layer disposed on the second region, in a second direction perpendicular to the upper surface of the substrate;
performing a high-temperature heat treatment process on the etch-stop layer; and
forming a plurality of first insulating patterns by implanting a first dopant into side surfaces of another portion of the channel supply layer, another portion of the channel layer, another portion of the separation layer, and a portion of the etch-stop layer, which are disposed on the first region, and forming second insulating patterns by implanting a second dopant into side surfaces of another portion of the etch-stop layer, a portion of the upper semiconductor layer, and a portion of the active layer, which are disposed on the second region.