US 12,087,849 B2
Semiconductor device
Yuichi Harada, Matsumoto (JP); Seiji Noguchi, Matsumoto (JP); Norihiro Komiyama, Matsumoto (JP); Yoshihiro Ikura, Matsumoto (JP); and Yosuke Sakurai, Azumino (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed by FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed on Jun. 24, 2021, as Appl. No. 17/356,585.
Application 17/356,585 is a continuation of application No. PCT/JP2020/020523, filed on May 25, 2020.
Claims priority of application No. 2019-141434 (JP), filed on Jul. 31, 2019.
Prior Publication US 2021/0320195 A1, Oct. 14, 2021
Int. Cl. H01L 29/739 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01)
CPC H01L 29/7397 (2013.01) [H01L 29/1095 (2013.01); H01L 29/407 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device that has a plurality of gate trench portions electrically connected to a gate electrode, and a plurality of dummy trench portions electrically connected to an emitter electrode, the plurality of gate trench portions comprising:
a first trench group that includes only one gate trench portion not adjacent any other gate trench portion, and two dummy trench portions which are provided adjacent to the only one gate trench portion and adjacent to each other; and
a second trench group that includes two gate trench portions adjacent to each other among the plurality of gate trench portions, wherein
the first trench group and the second trench group repeat in the semiconductor device according to a preset ratio.