US 12,087,833 B2
Semiconductor device and method for fabricating the same
Heon Bok Lee, Suwon-si (KR); Dae Yong Kim, Yongin-si (KR); Wan Don Kim, Seongnam-si (KR); Jeong Hyuk Yim, Seoul (KR); Won Keun Chung, Seoul (KR); Hyo Seok Choi, Hwaseong-si (KR); and Sang Jin Hyun, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 17, 2023, as Appl. No. 18/380,754.
Application 18/380,754 is a continuation of application No. 17/694,759, filed on Mar. 15, 2022, granted, now 11,799,004.
Application 17/694,759 is a continuation of application No. 16/695,675, filed on Nov. 26, 2019, granted, now 11,296,196, issued on Apr. 5, 2022.
Claims priority of application No. 10-2018-0152262 (KR), filed on Nov. 30, 2018.
Prior Publication US 2024/0063276 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/417 (2006.01); H01L 21/768 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/41775 (2013.01) [H01L 21/76897 (2013.01); H01L 29/0847 (2013.01); H01L 29/41791 (2013.01); H01L 29/6681 (2013.01); H01L 29/7851 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an active pattern on a substrate, the active pattern extending in a first direction;
a gate electrode on the active pattern, a longitudinal direction of the gate electrode extending in a second direction intersecting the first direction, and the gate electrode including a first portion and a second portion arranged adjacent to each other along the second direction;
a source/drain region in the active pattern on a sidewall of the gate electrode;
a source/drain contact connected to the source/drain region; and
a first contact plug connected to the source/drain contact on a sidewall of the first portion of the gate electrode, a portion of the first contact plug not overlapping with the source/drain contact,
wherein a height of a top surface of the first portion of the gate electrode is lower than a height of a top surface of the second portion of the gate electrode, and
wherein a height of a bottom surface of the first contact plug is higher than the height of the top surface of the first portion of the gate electrode.