US 12,087,825 B2
Metal oxide film and semiconductor device
Yasuharu Hosaka, Tochigi (JP); Toshimitsu Obonai, Tochigi (JP); Yukinori Shima, Gunma (JP); Masami Jintyou, Tochigi (JP); Daisuke Kurosaki, Tochigi (JP); Takashi Hamochi, Tochigi (JP); Junichi Koezuka, Tochigi (JP); Kenichi Okazaki, Tochigi (JP); and Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed on Sep. 8, 2023, as Appl. No. 18/243,850.
Application 18/243,850 is a continuation of application No. 17/370,221, filed on Jul. 8, 2021, granted, now 11,757,007.
Application 17/370,221 is a continuation of application No. 16/739,647, filed on Jan. 10, 2020, granted, now 11,063,125, issued on Jul. 13, 2021.
Application 16/739,647 is a continuation of application No. 16/152,850, filed on Oct. 5, 2018, granted, now 10,535,742, issued on Jan. 14, 2020.
Application 16/152,850 is a continuation of application No. 15/391,186, filed on Dec. 27, 2016, granted, now 10,096,684, issued on Oct. 9, 2018.
Claims priority of application No. 2015-257710 (JP), filed on Dec. 29, 2015; and application No. 2016-125478 (JP), filed on Jun. 24, 2016.
Prior Publication US 2023/0420522 A1, Dec. 28, 2023
Int. Cl. H01L 29/24 (2006.01); C03C 17/245 (2006.01); C04B 35/01 (2006.01); C04B 35/453 (2006.01); C04B 35/622 (2006.01); C23C 14/08 (2006.01); C23C 14/58 (2006.01); H01L 27/12 (2006.01); H01L 29/778 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/24 (2013.01) [C03C 17/245 (2013.01); C04B 35/01 (2013.01); C04B 35/453 (2013.01); C04B 35/62218 (2013.01); C23C 14/08 (2013.01); C23C 14/5853 (2013.01); H01L 27/1225 (2013.01); H01L 29/7782 (2013.01); H01L 29/7786 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); C03C 2217/23 (2013.01); C03C 2218/151 (2013.01); C04B 2235/3217 (2013.01); C04B 2235/3225 (2013.01); C04B 2235/3284 (2013.01); C04B 2235/3286 (2013.01); C04B 2235/3293 (2013.01); C04B 2235/787 (2013.01); C04B 2235/96 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first gate electrode over a substrate;
a first oxide semiconductor film over the first gate electrode;
a first source electrode and a first drain electrode over and in electrical contact with the first oxide semiconductor film;
a first conductive film;
a first insulating film over and in contact with a top surface of the first source electrode, a top surface of the first drain electrode, and a top surface of the first conductive film;
a second oxide semiconductor film over the first insulating film;
a second gate electrode over the second oxide semiconductor film;
a second conductive film;
a second insulating film over and in contact with a top surface of the second gate electrode and a top surface of the second conductive film;
a second source electrode and a second drain electrode over and in electrical contact with the second oxide semiconductor film; and
a pixel electrode over and in electrical contact with one of the second source electrode and the second drain electrode,
wherein the first gate electrode and the second conductive film overlap with each other, and
wherein the first conductive film and the second gate electrode overlap with each other.