US 12,087,818 B2
Transistor including two-dimensional (2D) channel
Minhyun Lee, Suwon-si (KR); Minsu Seol, Suwon-si (KR); and Hyeonjin Shin, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 17, 2022, as Appl. No. 17/967,200.
Application 17/967,200 is a continuation of application No. 17/111,965, filed on Dec. 4, 2020, granted, now 11,508,814.
Claims priority of application No. 10-2020-0007969 (KR), filed on Jan. 21, 2020.
Prior Publication US 2023/0031861 A1, Feb. 2, 2023
Int. Cl. H01L 29/10 (2006.01); H01L 29/36 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/1033 (2013.01) [H01L 29/36 (2013.01); H01L 29/4232 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transistor comprising:
a source electrode;
a drain electrode separated from the source electrode;
a gate electrode between the source electrode and the drain electrode;
a channel layer including a two-dimensional (2D) channel layer, the channel layer electrically contacting the source and drain electrodes;
a first doping layer on the 2D channel layer in a source region corresponding to the source electrode such that the source region of the 2D channel layer has a different doping concentration compared to a region of the channel layer adjacent to the source region; and
a second doping layer on the 2D channel layer in a drain region corresponding to the drain electrode such that the drain region of the 2D channel layer has a different doping concentration compared to a region of the channel layer adjacent to the drain region.