US 12,087,813 B2
Deep trench isolation with field oxide
Abbas Ali, Plano, TX (US); Rajni J. Aggarwal, Garland, TX (US); Steven J. Adler, Plano, TX (US); and Eugene C. Davis, McKinney, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 31, 2021, as Appl. No. 17/462,880.
Prior Publication US 2023/0060695 A1, Mar. 2, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 21/761 (2006.01); H01L 21/762 (2006.01); H01L 21/763 (2006.01)
CPC H01L 29/0649 (2013.01) [H01L 21/26513 (2013.01); H01L 21/76286 (2013.01); H01L 21/763 (2013.01); H01L 21/761 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating an electronic device, the method comprising:
forming a buried layer in at least a portion of a semiconductor substrate, the semiconductor substrate including majority carrier dopants of a first conductivity type, and the buried layer including majority carrier dopants of a second conductivity type;
forming a trench through a semiconductor surface layer and into one of the semiconductor substrate and the buried layer, the semiconductor surface layer including majority carrier dopants of the second conductivity type;
forming a dielectric liner along a sidewall of the trench from the semiconductor surface layer to the one of the semiconductor substrate and the buried layer;
forming polysilicon inside the trench and on the dielectric liner, the polysilicon filling the trench to a side of the semiconductor surface layer and including majority carrier dopants of the second conductivity type; and
forming a thermally grown field oxide on a portion of the side of the semiconductor surface layer, a portion of the thermally grown field oxide in contact with one of a portion of the dielectric liner and a portion of the polysilicon.