US 12,087,782 B2
Array substrate, display panel, and electronic device
Fei Ai, Wuhan (CN); Jiyue Song, Wuhan (CN); and Dewei Song, Wuhan (CN)
Assigned to WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Wuhan (CN)
Appl. No. 17/260,982
Filed by WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Wuhan (CN)
PCT Filed Nov. 24, 2020, PCT No. PCT/CN2020/131049
§ 371(c)(1), (2) Date Jan. 15, 2021,
PCT Pub. No. WO2022/088326, PCT Pub. Date May 5, 2022.
Claims priority of application No. 202011175784.3 (CN), filed on Oct. 28, 2020.
Prior Publication US 2022/0399383 A1, Dec. 15, 2022
Int. Cl. H01L 27/146 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G06F 3/041 (2006.01); G06V 40/13 (2022.01)
CPC H01L 27/14603 (2013.01) [G02F 1/13439 (2013.01); G02F 1/136227 (2013.01); H01L 27/14692 (2013.01); G02F 1/134363 (2013.01); G02F 1/13685 (2021.01); G06F 3/0412 (2013.01); G06V 40/1318 (2022.01); H01L 27/14612 (2013.01); H01L 27/14643 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a substrate comprising a control component;
a third metal layer disposed on the substrate, wherein the third metal layer comprises a first electrode and a first metal part, and the first electrode is connected to the control element through a first via;
a PIN diode disposed on the first electrode, wherein the PIN diode comprises a first semiconductor layer and an intrinsic semiconductor layer;
a third insulating layer disposed on the PIN diode;
a first conductive layer disposed on the third insulating layer, wherein the first conductive layer comprises a first connection part, and the first connection part is connected to the first metal part;
a fourth insulating layer disposed on the first conductive layer, wherein the fourth insulating layer is provided with a second via; and
a second conductive layer disposed on the fourth insulating layer and in the second via, wherein the second conductive layer comprises a second electrode, the second electrode covers the PIN diode, and the second electrode is connected to the first connection part through the second via;
wherein:
the substrate further comprises a switch element;
the fourth insulating layer is further provided with a third via;
the first conductive layer further comprises a second connection part, and the second connection part is connected to a drain of the switch element;
the second conductive layer further comprises a pixel electrode, and the pixel electrode is connected to the second connection part through the third via.