| CPC H01L 27/0886 (2013.01) [H01L 29/0669 (2013.01); H01L 29/7851 (2013.01)] | 20 Claims |
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1. An integrated circuit device, comprising:
a fin-type active region extending longitudinally in a first lateral direction on a substrate;
a nanosheet disposed at a position apart from a fin top surface of the fin-type active region in a vertical direction, and facing the fin top surface;
an inner insulating spacer between the substrate and the nanosheet;
a gate line including a main gate portion and a sub-gate portion, the main gate portion extending longitudinally in a second lateral direction on the nanosheet, the sub-gate portion being integrally connected to the main gate portion and between the substrate and the nanosheet, wherein the second lateral direction intersects with the first lateral direction; and
a source/drain region facing the sub-gate portion with the inner insulating spacer therebetween in the first lateral direction, the source/drain region being in contact with the inner insulating spacer and the nanosheet, the source/drain region including a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body toward an inside of the source/drain region,
wherein the at least one stacking fault surface comprises a plurality of stacking fault surfaces, and
wherein a density of the plurality of stacking fault surfaces increases toward a center of the source/drain region.
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