US 12,087,764 B2
Device integration schemes leveraging a bulk semiconductor substrate having a <111> crystal orientation
Mark Levy, Williston, VT (US); Jeonghyun Hwang, Ithaca, NY (US); and Siva P. Adusumilli, South Burlington, VT (US)
Assigned to GlobalFoundries U.S. Inc., Santa Clara, CA (US)
Filed by GlobalFoundries U.S. Inc., Santa Clara, CA (US)
Filed on Aug. 18, 2022, as Appl. No. 17/890,446.
Application 17/890,446 is a continuation of application No. 17/072,649, filed on Oct. 16, 2020, granted, now 11,469,225.
Prior Publication US 2022/0392888 A1, Dec. 8, 2022
Int. Cl. H01L 27/06 (2006.01); H01L 21/8258 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01)
CPC H01L 27/0605 (2013.01) [H01L 21/8258 (2013.01); H01L 27/0623 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/2003 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a bulk semiconductor substrate comprising a single-crystal semiconductor material having a <111>crystal orientation, the bulk semiconductor substrate having a first device region, and a second device region;
a bipolar junction transistor including a first terminal positioned in the single-crystal semiconductor material of the first device region of the bulk semiconductor substrate; and
a non-CMOS transistor in the second device region of the bulk semiconductor substrate, the non-CMOS transistor including a layer stack on the single-crystal semiconductor material of the bulk semiconductor substrate, and the layer stack including a layer comprising a III-V compound semiconductor material.